Altera Complete Design Suite v11.0 SP1-SPYRAL (Windows/Linux)

3950d796982d0f231f42f4c50fe306f9

Altera Complete Design Suite v11.0 SP1-SPYRAL (Windows/Linux) | 6.14 GB/8.21 GB

Quartus II software version 11.0, the industrys number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs is available for download. Quartus II software version 11.0 delivers the production release of Alteras new system level integration tool known as Qsys. The Qsys system integration tool saves time and effort in the FPGA design process by enabling faster system development and design reuse.

ModelSim Altera Edition is recommended for simulating all FPGA designs (Cyclone, Arria, and Stratix series FPGA designs)

DSP Builder technology allows you to go from system definition and simulation using the industry standard MathWorks Simulink tools to system implementation in a matter of minutes. The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore blocks and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation.

The Nios II Embedded Design Suite (EDS) is a collection of cutting edge software tools, utilities, libraries, and drivers to help you bring your design to market in record time.

Homepage: FPGA CPLD and ASIC from Altera



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