Xilinx ISE Design Suite ver. 13.3 .ISO - TBE [GFxSW]
Xilinx ISE Design Suite ver. 13.3 .ISO - TBE [GFxSW]
Xilinx ISE Design Suite ver. 13.3 .ISO - TBE [GFxSW] | 4.85 Gb
Xilinx introduced the ISE Design Suite software to enable breakthrough optimizations f power and cost with greater design productivity. F the first time, ISE design tools deliver intelligent clockgating technology that reduces dynamic power consumption by as much as 30 percent. The new suite also provides advances in timingdriven design preservation, AMBA 4 AXI4complaint IP suppt f plugandplay design, and an intuitive design flow with fourthgeneration partial reconfiguration capabilities that lowers system cost f a broad range of high perfmance applications.
With full production suppt f all Xilinx Virtex6 and Spartan6
FPGA families, the ISE release continues its evolution as the
industrys only domainspecific design suite with interoperable design
flows and tool configurations f logic, digital signal processing
(DSP), embedded processing, and systemlevel design. In addition, Xilinx
incpated a number of software infrastructure and methodology
enhancements that improve run time, streamline system integration, and
expand IP interoperability across its latest generation device families
and Targeted Design Platfms.
Intelligent Automation f Power Optimization
ISE Design Suite introduces the FPGA industrys first intelligent
clockgating technology with fully automated analysis and finegrain
(logic slice) optimization capabilities specifically developed to reduce
the number of transitions, a primary contributing fact of dynamic
power dissipation in digital designs. The technology wks by analyzing
designs using a series of unique algithms to detect sequential
elements...
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http://xilinx.com/tools/designtools.htm
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