Cadence SPB/OrCAD 16.5.000 (Allegro SPB) Hotfix SPB 16.50.005 - 16.50.007
Cadence SPB/OrCAD 16.5.000 (Allegro SPB) Hotfix SPB 16.50.005 - 16.50.007
| 2.19 GB 1.28 GB
Cadence SPB / OrCAD 16.50.000 is a comprehensive package of design of electronic circuits, analog and digital simulation, IC design of programmable logic and ASIC, as well as the development and preparation for the production of printed circuit boards.
Updates for Cadence SPB / OrCAD 16.50.004 - 16.50.006
To install the latest update, do not install everything, just download and install the latest. But in previous versions of SPB happened that after the upgrade appear "fresh" glitches, then try the previous one.
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
841096 APD WIREBOND Function required which to check wire not in die pad center.
903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
906692 ADW LRM LRM window is always in front when opening a project
912942 APD WIREBOND constraint driven wire bonding
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
932292 ADW LRM LRM crashes during Update operation on a customer design
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
932704 APD DEGASSING Shape > Degass never finishes on large GND plane
932871 APD GRAPHICS could not see cursor as infinite
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
933214 APD ARTWORK Film area report is larger when fillets are removed
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with or - signs.
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
934909 SCM UI Require support for running script on loading a design in SCM
935632 CAPTURE SCHEMATIC_EDITOR SHIFT Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
DATE: 09-16-2011 HOTFIX VERSION: 006
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
919822 TDA CORE Cannot configure LDAP to only list the login name
922907 ADW TDA olast_callout_fileo directive in the BOM section is empty causes tda for show Access Denied error
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
924448 F2B DESIGNVARI Design does not complete variant annotation
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
928738 PSPICE PROBE Y-axis grid settings for multiple plots
928748 PSPICE PROBE Cursor width settings not saved
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C Runtime Library error
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net not reconnected no longer happens
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
DATE: 08-31-2011 HOTFIX VERSION: 005
================================================== ================================================== ===============================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
================================================== ================================================== ===============================
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
916321 CAPTURE GEN_BOM letter limitation in include file
916907 CAPTURE SCHEMATICS oAuto Connect to Buso should place the wire through non-connectivity objects
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
922117 PSPICE PROBE Label colors are not correct in Probe
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 SPB16.3)
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
924458 SCM OTHER Project > Export > Schematics crashes
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
925435 CAPTURE TCL_INTERFACE Capture crashes if oSave design as UPPERCASEo option is disabled.
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
926503 CAPTURE GENERAL Memory leak Capture/Pspice
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
CadenceSPB16.5
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